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74VHC16244
16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)
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HIGH SPEED: tPD = 5.4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16244 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
TSSOP
ORDER CODES
PACKAGE TSSOP TUBE T&R 74VHC16244TTR
PIN CONNECTION
DESCRIPTION The 74VHC16244 is an advanced high-speed CMOS 16-BIT BUS BUFFER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. Any nG output control governs four BUS BUFFERS. Output Enable inputs (nG) tied together give full 16 bit operation. When nG is LOW, the outputs are enabled. When nG is HIGH, the output are in high impedance state. The device is designed to be used with 3-state memory address drivers, etc. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
February 2003
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74VHC16244
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1 2, 3, 5, 6 8, 9, 11, 12 13, 14, 16, 17 19, 20, 22, 23 24 25 30, 29, 27, 26 36, 35, 33, 32 41, 40, 38, 37 47, 46, 44, 43 48 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 SYMBOL 1G 1Y1 to 1Y4 2Y1 to 2Y4 3Y1 to 3Y4 4Y1 to 4Y4 4G 3G 4A1 to 4A4 3A1 to 3A4 2A1 to 2A4 1A1 to 1A4 2G GND VCC NAME AND FUNCTION Output Enable Input Data Outputs Data Outputs Data Outputs Data Outputs Output Enable Input Output Enable Input Data Outputs Data Outputs Data Outputs Data Outputs Output Enable Input Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOLS
TRUTH TABLE
INPUTS G L L H
X : Don't Care Z : High Impedance
OUTPUT An L H X Yn L H Z
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74VHC16244
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 75 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 0.3V) (VCC = 5.0 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V C ns/V
1) VIN from 30% to 70% of VCC
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DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 5.5 0 to 5.5 5.5 IO=-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA IO=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 0.1 4 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 2.5 1 40 Typ. Max. Value -40 to 85C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.55 0.55 5 1 40 A A A V V Max. -55 to 125C Min. 1.5 0.7VCC 0.5 0.3VCC V V Max. Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
VOH
II ICC
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74VHC16244
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3(*) 3.3(*) 5.0 tPZL tPZH Output Enable Time
(**)
Value TA = 25C Min. Typ. 5.3 7.8 3.6 5.4 Max. 8.4 11.9 6.0 8.0 10.6 14.1 7.3 9.3 14.0 9.2 1.5 1.0 -40 to 85C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 10.0 13.5 6.5 8.5 12.5 16.0 8.5 10.5 16.0 10.5 1.5 1.0 -55 to 125C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 10.0 13.5 7.0 9.0 12.5 16.0 8.5 10.5 16.0 10.5 1.5 1.0 ns ns ns Unit
CL (pF) 15 50 15 50 15 50 15 50 50 50 50 50 RL = 1K RL = 1K RL = 1K RL = 1K RL = 1K RL = 1K
tPLH tPHL
Propagation Delay Time
5.0(**) 3.3
(*)
6.6 9.1 4.7 6.2 10.3 6.7
3.3(*) 5.0(**) 5.0(**)
tPLZ tPHZ tOSLH tOSHL
Output Disable Time Output to Output Skew time (note 1)
3.3 5.0
(*)
(**)
3.3(*) 5.0(**)
ns
(*) Voltage range is 3.3V 0.3V (**) Voltage range is 5.0V 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 6 8 5.0 fIN = 10MHz 20 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit
CIN COUT CPD
Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/ 16(per Latch)
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74VHC16244
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 TA = 25C Min. Typ. 0.6 -0.9 CL = 50 pF 3.5 -0.6 Max. 0.9 V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
5.0
V
5.0
1.5
V
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
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74VHC16244
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 6.0 0.5 BSC 8 0.75 0 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
7065588C
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Tape & Reel TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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